Das IHP ist ein Institut der Leibniz-Gemeinschaft und betreibt Forschung und Entwicklung zu siliziumbasierten Systemen, Höchstfrequenz-Schaltungen und -Technologien einschließlich neuer Materialien. Es erarbeitet innovative Lösungen für Anwendungsbereiche wie die drahtlose und Breitbandkommunikation, Sicherheit, Medizintechnik, Industrie 4.0, Mobilität und Raumfahrt. Das IHP beschäftigt ca. 330 Mitarbeiterinnen und Mitarbeiter. Es verfügt über eine Pilotlinie für technologische Entwicklungen und die Präparation von Hochgeschwindigkeits-Schaltkreisen mit 0,13/0,25 µm-BiCMOS-Technologien, die sich in einem 1000 m² großen Reinraum der Klasse 1 befindet.

The position:
We invite applications for a PhD position focused on the development of a scalable, CMOS-compatible, and resourceefficient platform for integrating high-quality III–V multilayer device structures on Si and SOI substrates. The project addresses one of the central challenges in next-generation electronics and photonics: combining the superior optoelectronic properties of III–V semiconductors with the scalability and maturity of silicon technology.
As part of the Process and Device Research group within the Technology Department, you will investigate and advance selective epitaxy, stress-engineered growth concepts, and predictive growth modelling. The work spans fundamental materials science and applied process development, with direct relevance to future device integration.
A central element of the project is the adaptation of the selective epitaxy process to an 8-inch CMOS-compatible fabrication line, enabling controlled growth of InP virtual substrates on Si/SOI. You will study defect formation, nucleation mechanisms, and stress evolution in mismatched heterostructures, and use these insights to enable the re-growth of device-quality III–V multilayer stacks, including quantum wells and quantum dots.
You will join an international team of over 25 researchers, including senior scientists and PhD students, fostering a collaborative environment with flat hierarchies and strong mutual support. We value diversity and strive for a balanced gender mix, viewing a variety of perspectives as a significant asset to our team.

Key Responsibilities:

• Develop high-quality InP virtual substrates on Si and SOI, with precise control of defects, morphology, and stress
• Investigate InP nucleation on lattice-mismatched Si substrates and establish structure–property
  relationships
• Validate the first predictive growth model for InP nucleation, combining DFT simulations with experimental feedback
• Optimise InP virtual substrates to enable device-grade re-growth of complex III–V multilayer
  heterostructures
• Design and implement stress engineering strategies for multilayer stacks, including quantum wells and quantum dots
• Perform advanced structural and optical characterization to correlate growth conditions, morphology, composition, and defects with device-relevant properties
• Integrate developed processes into ongoing research projects and support experimental wafer runs
• Collaborate closely with internal experts and external academic and industrial partners

Your qualifications:
You hold a Master’s degree in Microelectronics, Materials Science, Physics, Chemistry, or a closely related field, and a solid understanding of semiconductor physics and materials science. Practical experience in a cleanroom environment, thin-film or epitaxial growth techniques such as MOVPE, MBE, or CVD is an advantage.
We are seeking a highly motivated candidate with a Master’s degree in Microelectronics, Materials Science, Physics, Chemistry, or a closely related field, and a solid foundation in semiconductor physics and materials science. You have gained practical experience in a cleanroom environment and have worked with thin-film or epitaxial growth techniques such as MOVPE, MBE, or CVD, or you are strongly motivated to develop these skills further during your PhD – this position is for you.
You are curious about heteroepitaxy, III–V semiconductor materials, and their integration into CMOS-compatible platforms, and you enjoy combining experimental work with scientific analysis. Experience with structural and optical characterization techniques (for example, XRD, SEM, TEM, AFM, photoluminescence, or Raman spectroscopy) will help you engage quickly with the project, and you will have the opportunity to deepen this expertise using state-ofthe-art infrastructure. Prior exposure to III–V materials, particularly InP-based heterostructures, as well as familiarity with selective epitaxy concepts, is advantageous but not required. Experience in strain and stress engineering,
advanced characterization (e.g. HRXRD, (S)TEM, cathodoluminescence), or computational modelling and simulation (DFT, FEM, or process modelling) is highly welcome and offers the possibility to combine theory and experiment.
As a strong team player, you should be capable of structuring your own work and bringing an organized and systematic approach to collaboration with creative minds. You are an ideal candidate if you possess experimental, analytical, and problem-solving skills, along with excellent communication abilities. The ability to quickly learn and operate the latest technical equipment and software is crucial. Proficiency in English is required, and knowledge of German is welcome.

Our Offer:
You will pursue your PhD in a dynamic, international research environment at the forefront of advanced semiconductor integration and epitaxy. The project combines fundamental research with strong technological relevance and offers excellent opportunities for high-impact publications, conference participation, and international collaboration. We support your scientific and professional development through structured onboarding, close supervision, and access to conferences, workshops, and advanced training. Flexible working hours and remote work options (where compatible with laboratory work) help ensure a healthy work-life balance, and we actively support
family-friendly working conditions.
IHP is TOTAL E-QUALITY-certified and committed to equal opportunities for all genders and groups. We strongly encourage applications from women and underrepresented groups. Qualified applicants with disabilities will be given preference in cases of equal suitability.
Join us and contribute to shaping the future of CMOS-compatible III–V device integration through rigorous science and collaborative research.